1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to an ovonic unified memory (OUM) or a magnetic random access memory (MRAM).
2. Description of the Background Art
In recent years, research and development have been proceeded with a new semiconductor memory device using a material employed in storage elements of a compact disk rewritable (CD-RW) or a digital versatile disk RAM (DVD-RAM) and so on. This semiconductor memory device employs a chalcogenide material (Gexe2x80x94Sbxe2x80x94Te based material: chalcogenide alloy) as a memory cell. The chalcogenide material turns into two states; an amorphous state (a high resistivity state) and a polycrystalline state (a low resistivity state) by heating and relevant cooling. The material exhibits different electric resistance values in the two states; therefore, discrimination on xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d can be performed by reading the states.
In order to turn the chalcogenide material into the crystalline state, the material is kept at a temperature less than 600xc2x0 C. for a period of the order of 10 ns. Thereafter, the material turns into a crystalline state by cooling. In order to turn the chalcogenide material into the amorphous state, the material is heated to a temperature of 600xc2x0 C. or more and then to cool rapidly.
While in a case of CD-RW or the like, the heating is performed using a laser, in a case where the chalcogenide material is used, the heating of the material is performed by feeding a current through a heating element to cause a change in its state. Such a semiconductor memory device includes: a chalcogenide film as a memory element; a resistor for heating the film; and a transistor selecting a memory cell, and the memory cell is called an OUM.
While there are various kinds of OUMs, there has been known one using a junction transistor (or a bipolar transistor) as the select transistor. The bipolar transistor, generally, has been known as an element capable of a high speed operation. The use of the bipolar transistor makes it possible to feed a current in an instant for the purpose of heating the chalcogenide material or to shut off a current in an instant for the purpose of cooling the chalcogenide material.
A semiconductor memory device using a bipolar transistor as a select transistor is disclosed in, for example, National Patent Publication No. 11-505071. FIG. 26 is a sectional view of a conventional semiconductor memory device disclosed in the above-mentioned publication. Referring to FIG. 26, a memory cell 420 includes a lower layer 412. Lower layer 412 includes an access device such as a diode or a bipolar transistor.
An electrode material layer 434 is formed on lower layer 412. A protective film 416 is formed on electrode material layer 434. A cell aperture 418 is formed in protective film 416. A pillar 444 is formed inside cell aperture 418. A side spacer 448 and a protrusion 446 are provided to pillar 444. A chalcogenide layer 426 is formed on protective film 416, side spacer 448 and protrusion 446. Electrode material layer 428 at the top is formed on chalcogenide layer 426.
In the above conventional memory cell 420, a bipolar transistor is formed in lower layer 412 extending laterally. Therefore, an area of the bipolar transistor as an access device increases, having resulted in a problem of difficulty in high integration of memory cells constituted of a chalcogenide material.
The present invention has been made in order to solve the above problem and it is accordingly an object of the present invention to provide a semiconductor memory device capable of achieving high integration.
A semiconductor memory device according to the present invention includes: a semiconductor substrate; a junction transistor formed on the semiconductor substrate; an insulating layer which has a hole accepting at least part of the junction transistor and reaching a surface of the semiconductor substrate, and which is formed on the semiconductor substrate; and a storage element electrically connected to part of the junction transistor provided in the hole. The storage element has a first state in which an electric resistance is relatively high and a second state in which an electric resistance is relatively low. The junction transistor includes: a first conductive type well region formed in said semiconductor substrate; a second conductive type impurity region formed in the first conductive type well region so as to face to the hole; and a first conductive type conductive region provided in the hole so as to be in contact with the second conductive type impurity region.
In the semiconductor memory device, with such a structure, according to the present invention, the junction transistor is connected to the storage element. Therefore, an electrical signal can be sent to the storage element at higher speed compared with a case where a field effect transistor or a diode is connected to the storage element. Furthermore, since at least part of the junction transistor is provided in the hole, an area occupied by the junction transistor on the semiconductor substrate decreases, thereby enabling higher integration.
Preferably, the first state includes an amorphous state and the second state includes a crystalline state. The first state includes an amorphous state and the second state includes a crystalline state. The semiconductor memory device further includes a first heating layer which is provided in the hole so as to interpose between the storage element and the first conductive type conductive region to have an electric resistance higher than that of the first conductive type conductive region, and which heats the storage element. In this case, by feeding a current to the first heating layer, the first heating layer is heated; therefore, enabling heating the storage element in a suitable manner by the heat.
Moreover, preferably, the semiconductor memory device further includes a second heating layer provided so as to isolate from the storage element to preheat the storage element. In this case, since the storage element is preheated by the second heating layer, the storage element can be heated in an instant. The semiconductor memory device further includes the plural junction transistors. The second conductive type impurity region is formed so as to extend in a prescribed direction. Each of the plural junction transistors share the second conductive type impurity region extending in the prescribed direction. In this case, since one second conductive type impurity region is shared by the plural junction transistors, the plural junction transistors can be formed in a narrower region compared with a case where the plural junction transistors have respective second conductive type impurity regions. The semiconductor memory device further includes a wiring layer which extends along the second conductive type impurity region, and which is electrically connected to the second conductive type impurity region. In this case, since the wiring layer is electrically connected to the second conductive type impurity region, reduction can be achieved in amount of a current flowing through the second conductive type impurity region. The semiconductor memory device further includes a second conductive type well region formed in the semiconductor substrate so as to surround the first conductive type well region. In this case, since the second conductive type well region surrounds the first conductive type well region, a potential in the first conductive type well region can be set to a proper value. In addition, the semiconductor memory device further includes a storage region including the plural storage elements and the plural junction transistors electrically connected to each of the plural storage elements. Each of the plural junction transistors include the plural second conductive type impurity regions extending in approximately parallel to each other. The second conductive type impurity regions of odd-numbers counting from the prescribed second conductive type impurity region among the plural second conductive type impurity regions are electrically connected to a first current driving unit provided on one end side of the storage region. The second conductive type impurity regions of even-numbers counting from the prescribed second conductive type impurity region are electrically connected to a second current driving unit provided on another end side of the storage region. In this case, since the odd-numbered second conductive type impurity regions and the even-numbered second conductive type impurity regions are connected to respective different current driving unit, a peripheral portion of the storage region can be compact. As a result, there can be provided a semiconductor memory device capable of achieving high integration.
Furthermore, preferably, the storage element includes: a first ferromagnetic material layer; an insulating layer formed on the first ferromagnetic material layer; and a second ferromagnetic material layer formed on the insulating layer. The first ferromagnetic material layer, the insulating layer and the second ferromagnetic material layer are provided in the hole.